A Pascal Machine Architecture Implemented in Bristle Blocks, a Prototype Silicon Computer

This thesis presents the multi-chip design of an architecture which directly implements the language Pascal. The design uses custom VLSl rather than standard chips in order to increase speed and reduce the number of chips needed. The integrated circuits comprising the architecture are designed using Bristle Blocks, a chip design tool developed at Caltech by Dave Johannsen (6). Bristle Blocks is called a silicon compiler because it will put together an entire integrated circuit from a high level description of its function. Bristle Blocks can be used to design datapath processor chips, where external microcode is used to control operations on data busses inside the chip. The Pascal machine architecture presented here is based on the EM-1 instruction set designed by Andrew Tannenbaum (11,13). The EM-1 instruction set is intended to allow efficient compilation of stack-based, high level languages. Tannenbaum supplies static frequency data which is used heavily in making design decisions in the Pascal machine architecture. VLSl design has several important differences from design using standard components. A large amount of function can be placed on a single chip, e.g., approximately 30,000 transistors on the Intel 8086, but only a small number of pins are available for off-chip communication (typically 64 or less). This requires designs to be highly modular. In the NMOS technology used at Caltech, driving signals off-chip takes up to ten times the time and energy of on-chip communication. This requires inter-chip communication to be limited as much as possible. Finally, the large amount of computing power available in VLSl encourages the use of concurrency to gain execution speed. This thesis is structured as follows. The thesis begins with a section defining the principles to be followed in designing the Pascal system architecture. Following that are sections describing Bristle Blocks and the EM-1 architecture. Next, the overall architecture of the Pascal machine is described, followed by sections detailing the system data busses, the common elements in the processors which make up the system, and the processors themselves. A conclusion section summarizes the work, provides a brief critique of Bristle Blocks, and includes recommendations for further work. Finally, the appendices document the Bristle Blocks datapath elements and the EM-1 instruction set

The VolumePro Real-Time Ray-Casting System

This paper describes VolumePro, the world’s first single-chip realtime volume rendering system for consumer PCs. VolumePro implements ray-casting with parallel slice-by-slice processing. Our discussion of the architecture focuses mainly on the rendering pipeline and the memory organization. VolumePro has hardware for gradient estimation, classification, and per-sample Phong illumination. The system does not perform any pre-processing and makes parameter adjustments and changes to the volume data immediately visible. We describe several advanced features of VolumePro, such as gradient magnitude modulation of opacity and illumination, supersampling, cropping and cut planes. The system renders 500 million interpolated, Phong illuminated, composited samples per second. This is sufficient to render volumes with up to 16 million voxels (e.g., 2563) at 30 frames per second.Engineering and Applied Science

Influenza in Migratory Birds and Evidence of Limited Intercontinental Virus Exchange

Migratory waterfowl of the world are the natural reservoirs of influenza viruses of all known subtypes. However, it is unknown whether these waterfowl perpetuate highly pathogenic (HP) H5 and H7 avian influenza viruses. Here we report influenza virus surveillance from 2001 to 2006 in wild ducks in Alberta, Canada, and in shorebirds and gulls at Delaware Bay (New Jersey), United States, and examine the frequency of exchange of influenza viruses between the Eurasian and American virus clades, or superfamilies. Influenza viruses belonging to each of the subtypes H1 through H13 and N1 through N9 were detected in these waterfowl, but H14 and H15 were not found. Viruses of the HP Asian H5N1 subtypes were not detected, and serologic studies in adult mallard ducks provided no evidence of their circulation. The recently described H16 subtype of influenza viruses was detected in American shorebirds and gulls but not in ducks. We also found an unusual cluster of H7N3 influenza viruses in shorebirds and gulls that was able to replicate well in chickens and kill chicken embryos. Genetic analysis of 6,767 avian influenza gene segments and 248 complete avian influenza viruses supported the notion that the exchange of entire influenza viruses between the Eurasian and American clades does not occur frequently. Overall, the available evidence does not support the perpetuation of HP H5N1 influenza in migratory birds and suggests that the introduction of HP Asian H5N1 to the Americas by migratory birds is likely to be a rare event

Language change for the worse

Many theories hold that language change, at least on a local level, is driven by a need for improvement. The present volume explores to what extent this assumption holds true, and whether there is a particular type of language change that we dub language change for the worse, i.e., change with a worsening effect that cannot be explained away as a side-effect of improvement in some other area of the linguistic system. The chapters of the volume, written by leading junior and senior scholars, combine expertise in diachronic and historical linguistics, typology, and formal modelling. They focus on different aspects of grammar (phonology, morphosyntax, semantics) in a variety of language families (Germanic, Romance, Austronesian, Bantu, Jê-Kaingang, Wu Chinese, Greek, Albanian, Altaic, Indo-Aryan, and languages of the Caucasus). The volume contributes to ongoing theoretical debates and discussions between linguists with different theoretical orientations

Virtual Machine Support for Many-Core Architectures: Decoupling Abstract from Concrete Concurrency Models

The upcoming many-core architectures require software developers to exploit concurrency to utilize available computational power. Today's high-level language virtual machines (VMs), which are a cornerstone of software development, do not provide sufficient abstraction for concurrency concepts. We analyze concrete and abstract concurrency models and identify the challenges they impose for VMs. To provide sufficient concurrency support in VMs, we propose to integrate concurrency operations into VM instruction sets. Since there will always be VMs optimized for special purposes, our goal is to develop a methodology to design instruction sets with concurrency support. Therefore, we also propose a list of trade-offs that have to be investigated to advise the design of such instruction sets. As a first experiment, we implemented one instruction set extension for shared memory and one for non-shared memory concurrency. From our experimental results, we derived a list of requirements for a full-grown experimental environment for further research

Custom Integrated Circuits

Contains reports on seven research projects.U.S. Air Force - Office of Scientific Research (Contract F49620-84-C-0004)National Science Foundation (Grant ECS81-18160)Defense Advanced Research Projects Agency (Contract NOO14-80-C-0622)National Science Foundation (Grant ECS83-10941

Custom Integrated Circuits

Contains reports on six research projects.U.S. Air Force - Office of Scientific Research (Contract F49620-84-C-0004)Analog Devices, Inc.Defense Advanced Research Projects Agency (Contract N00014-80-C-0622)National Science Foundation (Grant ECS83-10941

An estimate of carbon emissions from 2004 wildfires across Alaskan Yukon River Basin

© 2007 Tan et al; licensee BioMed Central Ltd. This is an Open Access article distributed under the terms of the Creative Commons Attribution Licens

Special Purpose Hardware for Design Rule Checking

Special purpose hardware can significantly increase the speed of integrated circuit design rule checking. The architecture described in this paper uses four custom chips to implement a raster scan DRC algorithm. It allows the use of 45° angles and can be programmed to check a wide variety of design rules involving an arbitrary number of layers. A shrink/expand operation allows the use of rasterization grids that are small relative to the minimum feature size. Using the Mead/Conway NMOS design rules and assuming a grid size of 1/2λ or 1/4 the minimum transistor width, this hardware can completely check a 3000λx3000λ layout in under a minute, if the input data can be provided quickly enough